1. Field of the Invention
The invention relates to a semiconductor non-volatile memory device, and more particularly to an improvement in an erasable and programmable read only memory device with a double-layered floating gate structure and a method for fabricating the same.
2. Description of the Related Art
Recently, developments of the erasable and programmable read only memory device with the double-layered floating gate structure and a flash memory device have been successful increasingly. The double-layered floating gate erasable and programmable read only memory device is classified in the group of the non-volatile memory device in which Fowler-Nordheim tunneling is utilized to accomplish the programming and erasure of data. One of the non-volatile memory devices utilizing the Fowler-Nordheim tunneling for programming and erasure of data is disclosed in 1992 IEDM Technical Digest pp. 991-993, H. Kume et al. in which a structure of the memory device is improved in a cell area by use of contactless cell array technique.
FIG. 1 is a conventional circuit configuration of the memory arrays The conventional memory arrays comprise a lateral alignment of a plurality of NOR memory cell array blocks "NOR". A plurality of global data lines D0, D1, . . . Dn run on the memory arrays in parallel to a longitudinal direction of the NOR memory cell array blocks "NOR". A plurality of word lines W0, W1, . . . , Wm run on the memory arrays in a vertical direction to the global data lines. First and second selective lines ST1 and ST2 run on the memory arrays in parallel to the word lines. Further, a common source line S runs on the memory arrays in a parallel direction to the word lines. Furthermore, first and second selective lines ST1 and ST2 also run on the memory arrays in a parallel direction to the word lines. Each of the NOR memory cell array blocks includes a plurality of double-layered floating gate memory transistors Q.sub.Mij serving as the erasable and programmable read only memory device. Each of the NOR memory cell array blocks further includes a pair of a local data line Ldn and a local source line Lsn. Each of the double-layered floating gate memory transistors Q.sub.Mij is provided between the local data line Ldn and the local source line Lsn wherein the local data line is connected to the drain side of each of the double-layered floating gate memory transistors Q.sub.Mij, while the local source line is connected to the source side of each of the double-layered floating gate memory transistors Q.sub.Mij. Each of the double-layered floating gate memory transistors Q.sub.Mij has both a control gate and the double-layered floating gate wherein the control gate is connected to the word line to receive control signals being transmitted on the word line and the floating gate stores a signal charge as data therein. The local data line is connected through a first selective transistor Qsn1 to the global data line Dn. The local source line is connected to a second selective transistor Qsn2 to the common source line S. The first and second selective transistors are provided in each of the NOR memory array blocks. The gates of the first and second selective transistors Qsn1 and Qsn2 are connected to the first and second selective lines ST1 and ST2 respectively.
FIG. 2 is a fragmentary plane view illustrative of the adjacent two NOR memory cell array blocks. FIGS. 3A and 3B are fragmentary cross sectional elevation views illustrative of the adjacent two NOR memory cell array blocks taken along A-A' line and B-B' line.
The NOR memory cell array blocks including the double-layered floating gate memory transistors is formed on a semiconductor substrate 201. Each of the double-layered floating gate memory transistors provided in a cell area surrounded by field oxide films 214 and isolation impurity diffusion regions 211a, 211b, 211c and 211d. The field oxide films 214 extend in parallel to the longitudinal direction of the NOR memory cell array blocks to isolate the adjacent two NOR memory cell array blocks from each other, while the isolation impurity diffusion region 211a, 211b, 211c and 211d extend in parallel to the word lines to isolate the double-layered floating gate memory transistors involved in each the NOR memory cell array blocks from each other. The double-layered floating gate memory transistors have source and drain regions 204a, 204b, 204c and 204d formed in upper regions of the semiconductor substrate 201. A gate oxide film 202 is provided on the semiconductor substrate 201 in a predetermined area defined by the field oxide films 214 to extend over the source and drain regions and the isolation impurity diffusion regions. First floating gates 203a, 203b, 203c and 203d are provided through the gate oxide film 202 over channel regions define by the source and drain regions and the isolation impurity diffusion regions. The first floating gates 203a, 203b, 203c and 203d are surrounded by a first inter-layer insulator 205. Second floating gates 206a, 206b, 206c and 206d extend on the first floating gates 203a, 203b, 203c and 203d and further extend in the parallel direction to the word lines on the first inter-layer insulator 205. The first and second floating gates are in contact with each other to form a double-layered floating gate structure. A second gate oxide film 209 is provided on the second floating gate and further extends in the parallel direction to the word lines. A control gate 210 is provided on the second gate oxide film 209 to extend in the parallel direction to the word lines. A second inter-layer insulator 212 is provided on an entire region to cover the control gate 210 and also to isolate individual gate structures comprising the control gate and the double-layered floating gates from each other in parallel to the data lines. Metal wirings 213 are provided on the second inter-layer insulator 212 in the longitudinal direction of the NOR memory cell array blocks. The metal wirings 213 may serve as the data lines. In FIG. 2, a filed pattern 220 is defined by the field oxide film 214.
The first gate oxide film 202 is very thin, for example, 100 angstroms and further the second floating gate 206 extends beyond the area of the first floating gate 203 to have a larger contact area than a contact area of the first floating gate 203 so that a capacitance between the control gate 210 and the second floating gate 206 is larger than a capacitance between the first floating gate 203 and the semiconductor substrate 201. This structure may permit that a Fowler-Nordheim tunneling between the first floating gate 203 and either the source or drain regions is caused by applying the control gate 210 with a relatively low voltage, for example, 3 V. The Fowler-Nordheim tunneling between the first floating gate 203 and either the source or drain regions may be utilized for data erasure and programming.
The description will focus on operations of the memory devices with reference back to FIG. 1, provided that each of the double-layered floating gate memory transistors is an n-channel transistor. The following Table 1 describes a relationship of selections of the double-layered floating gate memory transistors and voltages of any lines involved in the memory arrays, for example, voltages of the first and second selective lines ST1 and ST2, the word lines W0, W1, W2 and Wm, the global data line D0, the local data line Ld0, the local source line Ls0 and the common source line S.
TABLE 1 __________________________________________________________________________ Mode Erase Write Read Tr -- Q.sub.M00 Q.sub.M01 Q.sub.M02 Q.sub.M0m Q.sub.M00 Q.sub.M01 Q.sub.M02 Q.sub.M0m __________________________________________________________________________ ST1 3 3 3 W0 13 -9 3 3 3 3 0 0 0 W1 13 3 -9 3 3 0 3 0 0 W2 13 3 3 -9 3 0 0 3 0 Wm 13 3 3 3 -9 0 0 0 3 D0 0 3 1 Ld0 0 3 1 Ls0 0 floating 1 ST2 3 0 3 S 0 0 0 __________________________________________________________________________ (Unit : V)
The data erasure is accomplished by injection of electrons into the floating gate, while the data programming or write operation is accomplished by extraction of electrons from the floating gate.
The following descriptions will be concerned with the mode of data erasure of the memory transistors Q.sub.M00, Q.sub.M01, Q.sub.M02 and Q.sub.M0m. When a data erasure of the memory transistor Q.sub.00 is required, a voltage of the global data line D0 is set at 0 V and a voltage of the first selective line ST1 is set at 3 V thereby the first selective transistor Q.sub.s01 turns ON. During this mode, a voltage of the global data line D0 is kept at 0 V so that the 0 V of the global data line D0 is applied on the local data line L.sub.Dn. A voltage of the second selective line ST2 is set at 3 V thereby the second selective transistor Q.sub.s02 turns ON. During this mode, a voltage of the common source line S is also held at 0 V so that the 0 V of the common source line S is applied on the local source line L.sub.sn. In this meantime, all of the word lines involved in the memory arrays are applied with a high voltage, for example, 13 V. That is why the control gate of each of the memory transistors involved in the memory arrays receives the high voltage of 13 V. The first gate oxide film 202 is designed to be thinner than the second gate oxide film 209 so that a relatively high electric filed is caused in the first gate oxide film 202 between the double-layered floating gate structure and the semiconductor substrate 201. The electric filed caused in the first gate oxide film 202 is sufficiently high to cause a Fowler-Nordheim tunneling that may inject electrons in the channel region through the first gate oxide film 202 to the first floating gate 203 as illustrated in FIGS. 4B and 5. The electron injection into the first floating gate, that was caused by the Fowler-Nordheim tunneling, results in an increase of a threshold voltage of the individual memory transistor. The injection of the electrons into the first floating gate may complete the data erasure of the memory transistor.
When it is required to store the data in the memory transistor without erasure of the data, the word line is applied with a 0 V.
Consequently, when the data erasure of the memory transistor is required, the local source and drain lines are applied with 0 V to render the source and drain regions of the transistor have 0 V and further a high voltage such as 13 V is applied to the control gate of the memory transistor to case the Fowler-Nordheim tunneling that cause the electron injection from the channel region through the first gate oxide film into the first floating gate.
Operations in the data writing mode or the programming mode will be described. When a data writing or programming to the memory transistor Q.sub.M00 is required, the voltage of the global data line D0 is set at 3 V. The first selective line ST1 is also set at a voltage of 3 V to have the first selective transistor turn ON to thereby permit the voltage of 3 V on the global data line to be applied on the local data line. By contrast, the common source line is set at a voltage of 0 V to have the second selective transistor turn OFF to thereby place the local source line in the floating state. Under the above states, the word lines are set at a negative voltage, for example, -9 V That is why the control gate of each of the memory transistors involved in the memory arrays receives the negative voltage of -9 V. The first gate oxide film 202 is thinner than the second gate oxide film 209 so that a relatively high electric filed is caused in the first gate oxide film 202 between the double-layered floating gate structure and the semiconductor substrate 201. The electric filed caused in the first gate oxide film 202 is sufficiently high to cause a Fowler-Nordheim tunneling that may extract electrons from the first floating gate to have the extracted electrons be injected through the first gate oxide film 202 into the drain region of the memory transistor as illustrated in FIGS. 4A and 5. The electron extraction from the first floating gate, that was caused by the Fowler-Nordheim tunneling, results in a drop of the threshold voltage of the individual memory transistor. The extraction of the electrons from the first floating gate may complete the data writing or programming of the memory transistor.
When it is required to store the data in the memory transistor without writing of the data, the word line is set at the positive voltage, for example, 3 V.
Consequently, when the data writing or the programming of the memory transistor is required, the local source region is made into the floating state and the drain region is set at the voltage of 3 V and further a negative voltage such as -9 V is applied to the control gate of the memory transistor to case the Fowler-Nordheim tunneling that causes the electron extraction from the floating gate through the first gate oxide film into the drain region.
Operations in mode of reading the data already stored in each of the memory transistors Q.sub.M00, Q.sub.M01, Q.sub.M02 and Q.sub.M0m will subsequently described. When a read operation of the data from the memory transistor Q.sub.M00, then the global data line D0 is set at a voltage of 1 V and the first selective line ST1 is set at 3 V and also the second selective line is set at a voltage of 3 V. The common source line S is set at a voltage of 0 V. As a result, the first and second memory transistors turn ON thereby the local data line is applied with the voltage of 1 V and the local source line is applied with a voltage of 0 V. The word line W0 being connected to the control gate of the memory transistor Q.sub.M00, from which the stored data should be red out, is set at a voltage of 3 V, while the remaining word lines W1, W2 and Wm being not connected to the control gate of the memory transistor Q.sub.M00 are set at a voltage of 0 V.
Under the above state, if the memory transistor Q.sub.M00 is in the erasure state, then electrons exist in the floating gate thereby the threshold voltage is higher than the voltage applied on the word line connected to the control gate of the memory transistor. This results in no current from the global data line to the common source line.
By contrast, if the memory transistor Q.sub.M00 is in the data writing or programming state, then no electron exist in the floating gate thereby the threshold voltage is lower than the voltage applied on the word line connected to the control gate of the memory transistor. This results in a current flow from the global data line to the common source line.
The description will focus on the bias states both in the data erasure mode and in the data programming mode. The following Table 2 describes voltages of the first and second selective lines ST1 and ST2, the word line W0, the global data lines D0 and D1, the local data lines Ld0 and Ld1, the local source lines Ls0 and Ls1 and the common source line S.
TABLE 2 ______________________________________ Mode Erase Write Tr -- Q.sub.M00 Q.sub.M10 ______________________________________ ST1 3 3 W0 13 -9 D0 0 3 0 D1 0 0 3 Ld0 0 3 0 Ld1 0 0 3 Ls0 0 floating floating Ls1 0 floating floating ST2 3 0 S 0 0 ______________________________________ (Unit : V)
The control gates of the memory transistors Q.sub.M00 and Q.sub.M10 are connected to the word line W0, for that reason the erasure mode is free from any selectivity of the memory transistors, but in the write mode a selective writing operation is carried out by voltage controls of the local data lines Ld0 and Ld1.
The following descriptions are concerned with operations when writing the data into the memory transistor Q.sub.M00 only, but not writing any data into the memory transistor Q.sub.M10. The memory transistor Q.sub.M00 only comes into a bias state, while due to no writing operation of the memory transistor Q.sub.M10, the global data line is set at a voltage of 0 V to make the local data line have the voltage of 0 V. When the memory transistor Q.sub.M00 is in the bias state, the control gate of the memory transistor Q.sub.M00 is applied with a negative voltage of 9 V and the drain thereof receives a positive voltage of 3 V. By contrast, the drain of the memory transistor Q.sub.M10 is applied with a zero voltage. Then, the memory transistor Q.sub.M10 has a low electric field between the control gate and the drain region than an electric field between those of the memory transistor Q.sub.M00. That is why the memory transistor Q.sub.M10 has no appearance of the Fowler-Nordheim tunneling, even while the memory transistor Q.sub.M00 shows the Fowler-Nordheim tunneling. No appearance of the Fowler-Nordheim tunneling may prevent any writing operation.
From the above descriptions, it could be understood that the conventional memory transistor utilizes the Fowler-Nordheim tunneling for data programming and data erasure operation. In the conventional memory transistor, the plural memory transistors are connected through those drains to a single local data line that is further connected through the first selective transistor to the global data line as well as the memory transistors are connected through those sources to a single local source line that is further connected through the seond selective transistor to the common source line. The plural memory transistors and the first and second selective transistors may constitute a single NOR memory cell array block. The memory transistors connected to one of the word lines are separated through the field oxide films from each other. The isolation by the field oxide film of the memory cell array blocks may raise a problem with a generation of a bird's beak in the fabrication process. The bird's beak provides an enlargement of the isolation region thereby resulting in a reduction of the cell size in the parallel direction to the word lines.
A method for settling the above problem with the bird's beak was proposed and disclosed in the Japanese laid-open patent application No. 2-87677. The method will be described with reference to FIGS. 6A to 6F.
With reference to FIG. 6A, a semiconductor substrate 301 is prepared before a filed oxide film 314 and a first gate oxide film 302 are formed on a surface of the semiconductor substrate 301 wherein the first gate oxide film is formed on a memory cell region. A floating gate is formed by use of patterning in the memory cell region on the first gate oxide film 302.
With reference to FIG. 6B, a photo resist mask 316 is formed by patterning on a surface of the device except for an isolation region for isolating memory cell regions from each other.
With reference to FIG. 6C, the floating gate 315, the first gate oxide film 302 and the semiconductor substrate 301 are sequentially removed by etching with use of the photo resist pattern as a mask to form isolation trench grooves 307, after that the used photo-resist mask are removed from the semiconductor substrate 301.
With reference to FIG. 6D, a thermal oxidation is carried out so that a second gate oxide film 309 is formed over the floating gate 315 and a side wall isolation film is formed on side walls and a bottom of the isolation trench groove as well as a gate oxide film is formed on a peripheral transistor region. An isolation film is deposited by a chemical vapor deposition within the trench grooves for subsequent etchback process to fill the trench grooves with a trench groove isolation film 308.
With reference to FIG. 6E, a control gate 310 comprising a polysilicon film is formed and then receive a thermal oxidation so that a thin isolation film 317 is formed to cover the control gate 310.
With reference to FIG. 6F, diffusion regions 304 are formed in an upper region of the semiconductor substrate 301 in the peripheral transistor region. Other diffusion regions not illustrated are also formed in an upper region of the semiconductor substrate 301 but in the memory transistor region. Further, an inter-layer insulator 318 is formed on the surface of the device, after which metal wirings 313 are formed on the inter-layer insulator 318.
Consequently, that prior art utilizes the isolation trench groove to isolate the memory cell transistors from each other and also utilizes the self-alignment technique of the channel regions of the memory cell transistors by defining the trench isolation. Notwithstanding, that prior art is not applicable to the fabrication processes of the double-layered floating gate memory transistor. If that prior art is applied to the fabrication processes of the double-layered floating gate memory transistor, then the isolation region extends to the source and drain regions of the memory transistors so the required source and drain regions are not formed. Then, the double-layered floating gate memory transistors formed by the conventional method as disclosed in the Japanese laid-open patent application No. 2-87677 could not be operational. Consequently, any prior arts that has been known in the art could not settle the problems with the enlargement of the isolations regions that renders the cell region small.